1. Field of the Invention
The present invention relates to a packet command driving type memory device, particularly, to a method for compressing output data that can reduce test time and determine an exact position where a memory failure occurs and a memory device having a pre-fetched data output structure.
2. Description of Related Art
In a prior packet command driving type memory device, e.g., a memory device such as a RAMBUS DRAM, a data pass structure is depicted in FIG. 1. FIG. 2 shows details of part A (a dotted line part) of FIG. 1, with data passing through from a core cell region 10 to an output pad DQ.
During a write operation, individual data bits are transferred to an interface part 40 and are packed into 8-bit packets, each of which is packed during 4 clock cycles timed at a negative edge and a positive edge of each clock cycle per data pad (DQA0–DQA7, DQB0–DQB7). Even bits (i.e., 0, 2, 4, 6) of the 8-bit data packeted during 4 clock cycles, for example, are transferred to a data input/output part 30 via an interface part 40 at an ascending edge of a clock signal tclk. Odd bits (i.e., 1, 3, 5, 7), for example, are transferred to the data input/output part 30 via the interface part 40 at a descending edge of a clock signal tclk.
The 8-bit data transferred via the interface part 40 are transformed to parallel data of 8 bits WD<0:7> through a data input shift part (not shown in the drawing) of the data input/output part 30, transferred to the core cell region 10 via a column control part 20, and written in a packet form. During a read operation, an 8-bit packet RD<0:7> is read from the core cell region 10, transferred to the data input/output part 30 via the column control part 20. The data input/output part 30 transforms data in packet form to an even-bit part and an odd-bit part via shift registers 31–34. Multiplexer and the drivers 41–44 of the interface part 40 transfer even data bits eread<0, 2, 4, 6> to data pads at an ascending edge of each clock signal tclk and Odd data bits oread<1, 3, 5, 7> to data pads at a descending edge of each clock signal tclk. Accordingly, 8 bits are transferred from a packet form to a serial form via respective data pads (DQA0–DQA7, DQB0–DQB7) during 4 clock cycles.
A prior memory device having a data pass structure as described above prefetches data by 8 bits from the core cell region 10, and then outputs the data at the ascending edge and the descending edge of each of the four clock cycles via a shift register of the data input/output part 30.
Such a prior memory device having a data pass structure as described above checks the output of every individual output data pad and detects a failure of the memory device in a DA test mode. Since each data output pad is separately associated with each output data pin it is not efficient for testing purposes. For example, if the number of pins allocated for outputting data of a tester is N and when the number of data output pads of a device is 16, the maximum number of devices that can be tested simultaneously is N/16.
A prior memory device may also compare data read from the core cell region 10 via a read data comparing part, determines whether a failure of the memory device has occurred, and outputs the result (Error_out) via an output terminal SI01. However, although a prior memory device could discriminate whether a failure has occurred by comparing the read data, the problem is that in a wafer level test, one cannot determine where in the core cell region 10 the failure occurred. Hence, one has to seek to repair the cell.